Many high-speed integrated circuit devices, such as synchronous dynamic random access memories (SDRAM), rely upon clock signals to control the flow of commands, data, and addresses into, through, and out of the devices. Typically, operations are initiated at edges of the clock signals (i.e., transitions from high to low or low to high). To more precisely control the timing of operations within the device, each period of a clock signal is sometimes divided into subperiods so that certain operations do not begin until shortly after the clock edge.
One method for controlling the timing of operations within a period of a clock signal generates phase-delayed versions of the clock signal. For example, to divide the clock period into four subperiods, phase delayed versions are produced that lag the clock signal by 90.degree., 180.degree. and 270.degree., respectively. Edges of the phase-delayed clock signals provide signal transitions at the beginning or end of each subperiod that can be used to initiate operations.
An example of such an approach is shown in FIGS. 1 and 2 where the timing of operations in a memory device 10 is defined by an externally provided reference control clock signal CCLKREF and an externally provided reference data clock signal DCLKREF. The reference clock signals CCLKREF, DCLKREF are generated in memory controller 11 and transmitted to the memory device 10 over a command clock bus and a data clock bus. The reference clock signals CCLKREF, DCLKREF have identical frequencies, although the reference control clock signal CCLKREF is a continuous signal and the reference data clock signal DCLKREF is a discontinuous signal, i.e., the reference data clock signal DCLKREF does not include a pulse for every clock period T, as shown in FIG. 2. Although the reference clock signals CCLKREF, DCLKREF have equal frequencies, they may be phase shifted by a lag time T.sub.L upon arrival at the memory device 10 due to differences in propagation times, such as may be produced by routing differences between the command clock bus and the data clock bus.
Control data CD1-CDN arrive at respective input terminals 12 substantially simultaneously with pulses of the reference control clock signal CCLKREF and are latched in respective control data latches 16. However, if the device attempts to latch the control data CD1-CDN immediately upon the edge of the reference clock signal CCLKREF, the control data may not have sufficient time to develop at the input terminal 12. For example, a voltage corresponding to a first logic state (e.g., a "0") at the input terminal 12 may not change to voltage corresponding to an opposite logic state (e.g., a "1") by the time the data are latched. To allow time for the control data CD1-CDN to develop fully at the input terminal 12, the control data are latched at a delayed time relative to the reference control clock signal CCLKREF. To provide a clock edge to trigger latching of the commands CD1-CDN at the delayed time t.sub.1, a delay circuit 18 delays the reference clock signal CCLKREF by a delay time T.sub.D1 to produce a first delayed clock signal CCLKD. Edges of the first delayed clock signal CCLKD activate the control data latches to latch the control data CD1-CDN at time t.sub.1.
Data DA1-DAM arrive at the data terminals 14 substantially simultaneously with the reference data clock signal DCLKREF, as shown in the fourth and fifth graphs of FIG. 2. Respective data latches 20 latch the data DA1-DAM. As with the control data CD1-CDN, it is desirable that the data DA1-DAM be latched with a slight delay relative to transitions of the reference data clock DCLKREF to allow time for signal development at the data terminals 14. To provide a delayed clock edge, a delay block 22 delays the reference data clock signal DCLKREF to produce a phase-delayed data clock DCLK1 that is delayed relative to the reference data clock signal DCLKREF by the delay time T.sub.D1.
For latching both control data CD1-CDN and data DA1-DAM, it is often desirable to allow some adjustment of the phase delay. For example, if the clock frequencies change, the duration of the subperiods will change correspondingly. Consequently, the delayed clocks CCLKD, DCLKD may not allow sufficient signal development time before latching the control data or data. Also, variations in transmission times of control data, data, or clock signals may cause shifts in arrival times of control data CD1-CDN or data DA1-DAM relative to the clock signals CCLKREF, DCLKREF of the memory device.
One possible approach to producing a variable delay control clock CCLKD employs a delay-locked loop 38 driven by the reference command clock CCLKREF, as shown in FIG. 3. The reference control clock signal CCLKREF is input to a conventional multiple output variable delay circuit 40 such as that described in Maneatis, "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques," IEEE Journal of Solid-State Circuits 31(11):1723-1732, November 1996. The delay circuit 40 is a known circuit that outputs multiple delayed signals CCLK1-CCLKN with increasing lags relative to the reference signal CCLKREF. The delays of the signals CCLK1-CCLKN are variable responsive to a control signal V.sub.CON received at a control port 42.
A feedback circuit 44 formed from a comparator 46 and an integrator 48 produces the control signal V.sub.CON. The feedback circuit 44 receives the reference control clock signal CCLKREF at one input of the comparator 46 and receives one of the output signals CCLKN from the delay circuit 40 as a feedback signal at the other input of the comparator 46. The comparator 46 then outputs a compare signal V.sub.COMP that is integrated by the integrator 48 to produce the control signal V.sub.CON.
As is known, the control signal VCON will depend upon the relative phases of the reference control clock signal CCLKREF and the feedback signal CCLKN. If the feedback signal CCLKN leads the reference control clock signal CCLKREF, the control signal V.sub.CON increases the delay of the delay circuit 40, thereby reducing the magnitude of the control signal V.sub.CON until the feedback signal CCLKN is in phase with the reference signal CCLKREF. Similarly, if the feedback signal CCLK lags the reference signal CCLKREF, the control signal V.sub.CON causes the delay circuit 40 to decrease the delay until the feedback voltage CCLKN is in phase with the reference voltage CCLKREF.
A similar delay-locked loop 50 produces the delayed data clock signals DCLK1-DCLKN in response to the reference data clock signal DCLKREF. However, unlike the reference control clock signal CCLKREF, the reference data clock signal DCLKREF is discontinuous. Typically, the reference data clock signal DCLKREF arrives in bursts of clock pulses as a block of data is accessed. Between bursts, the reference data clock signal DCLKREF is relatively inactive such that the delay-locked loop 50 may lose its lock. Consequently, when bursts arrive, the delays of the delayed data clocks DCLK1-DCLKN may not be properly adjusted by the delay-locked loop 50 and the data DA1-DAM may have insufficient or excessive development time at the data bus before latching.